1. Field of the Invention
The present invention relates to a layered chip package that includes a plurality of chips stacked and a method of manufacturing the same.
2. Description of the Related Art
In recent years, a reduction in weight and an improvement in performance have been demanded of mobile devices typified by cellular phones and notebook personal computers. Accordingly, there has been a demand for higher integration of electronic components for use in mobile devices. Higher integration of electronic components has been demanded also for achieving an increase in capacity of semiconductor memory.
As an example of highly integrated electronic components, a system-in-package (hereinafter referred to as SiP), especially an SiP utilizing a three-dimensional packaging technology for stacking a plurality of semiconductor chips, has attracting attention in recent years. In the present application, a package that includes a plurality of semiconductor chips (hereinafter, also simply referred to as chips) stacked is called a layered chip package. Since the layered chip package allows a reduction in wiring length, it provides the advantage of allowing a higher operation speed for circuits and a reduction in stray capacitance of wiring, as well as the dvantage of allowing higher integration.
Major examples of the three-dimensional packaging technology for fabricating a layered chip package include a wire bonding method and a through electrode method. According to the wire bonding method, a plurality of chips are stacked on a substrate, and a plurality of electrodes formed on each chip are connected to external connecting terminals formed on the substrate by wire bonding. According to the through electrode method, a plurality of through electrodes are formed in each of the chips to be stacked and inter-chip wiring is performed through the use of the through electrodes. U.S. Patent Application Publication No. US 2008/0179728 A1 describes a laminated memory formed using the through electrode method.
The wire bonding method has the problem that it is difficult to reduce the distance between the electrodes so as to avoid contact between wires, and the problem that the high resistances of the wires hinder the acceleration of operation of circuits. The through electrode method is free from the problems of the wire bonding method.
For a wafer to be cut into a plurality of chips, the yield of the chips, that is, the rate of conforming chips with respect to all chips obtained from the wafer, is 90% to 99% in many cases. Since a layered chip package includes a plurality of chips, the rate of layered chip packages in which all of the plurality of chips are conforming ones is lower than the yield of the chips. The larger the number of chips included in each layered chip package, the lower the rate of layered chip packages in which all of the chips are conforming ones.
A case will now be considered where a memory device such as a flash memory is formed using a layered chip package. For a memory device such as a flash memory, a redundancy technique of replacing a defective column of memory cells with a redundant column of memory cells is typically employed so that the memory device can normally function even when some memory cells are defective. In the case where a memory device is formed using a layered chip package, the redundancy technique is also employable to make it possible that, even if some of memory cells included in any chip are defective, the memory device can normally function while using the chip including the defective memory cells. Assume, however, that a chip including a control circuit and a plurality of memory cells has become defective due to, for example, a wiring failure of the control circuit, and it does not function normally even by employing the redundancy technique. In such a case, the defective chip is no longer usable. While the defective chip can be replaced with a conforming one, it increases the cost for the layered chip package.
US 2007/0165461 A1 discloses a technique of identifying one or more defective flash memory dies in a flash memory device having a plurality of flash memory dies, and disabling memory access operations to each identified die.
The technique disclosed in US 2007/0165461 A1 is applicable to the case where a memory device is formed using a layered chip package, so that one or more defective chips included in the layered chip package can be identified and disabled.
In the case of a layered chip package formed using the through electrode method, however, disabling a defective chip produces the following problem. In the layered chip package formed using the through electrode method, the circuit in each chip is electrically connected to a plurality of through electrodes that are formed in the chip. In every two vertically adjacent chips, the plurality of through electrodes of one of the two chips are electrically connected to the respective corresponding through electrodes of the other of the two chips. The circuit in each chip is then electrically connected to a plurality of external terminals of the layered chip package via the plurality of through electrodes of one or more chips. Even if a defective chip is disabled in such a layered chip package, the circuit in the defective chip is still electrically connected to the plurality of external terminals of the layered chip package. In such a case, the circuit in the defective chip can produce capacitances and inductances that are unnecessary for a device to be implemented by the layered chip package, such as a memory device. This hinders the acceleration of operation of the device such as a memory device.